This course introduces high-performance computer architecture in a systemic manner. It discusses instruction set architecture design and computer performance evaluation methodology. It introduces techniques that allow a processor to exploit instruction-level parallelism in a sequential program and reduce its execution time, including pipelining, dynamic instruction scheduling, and branch prediction. It discusses the memory hierarchy, cache optimization techniques, and DRAM memory system designs. Those techniques target at reducing the performance loss due to the wide CPU-memory speed gap. Finally, it briefly introduces techniques to improve performance beyond instruction-level parallelism, including multi-core and multi-threaded processors.
School of Engineering and Computing
Electrical Engineering Technology (ELT)
3 hours of lecture per week